I've been doing some more reading on how Throttleblaster works and how other throttling methods work.
Per the Intel 64 and IA-32 Architecture Software Developer's Manual, they do mention ODCM throttling with respect to Pentium 4 and P6 architecture.
Regarding the Pentium 4 they state:
Modulation of duty cycles is processor model specific. Note that the processors STPCLK# pin is not used here; the stop-clock circuitry is controlled internally.
This was also noted in the CPUSPD tool thread. And it makes sense that this is software controllable via CPUSPD for processors like the Pentium 4, D, and Core 2.
For P6 processors (e.g. Pentium Pro, PII, PIII), they state:
For the P6 family processors, on-demand clock modulation was implemented through the chipset, which controlled clock modulation through the processor’s STPCLK# pin.
Reading up on how Trottleblaster functions, it sounds like it doing exactly that: introducing halt states at specified intervals via the STPCLK# pin. The main difference is that it is being controlled externally via a micro controller and therefore allows for more granular control over the frequency.
From the sounds of it, Throttleblaster is just ODCM throttling done via hardware instead of internally like on a Pentium 4.