GloriousCow wrote on 2024-02-24, 18:27:But is this updated per cycle? A DMA transfer may not be active when the CPU begins an instruction, but sometime after, and imp […]
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superfury wrote on 2024-02-24, 18:04:
UniPCemu's CPU and DMA both use the same kind of memory handling basically. Stuff like delays are handled in exactly the same way (with regards to the waitstates at least).
The CPU checks when starting any memory transfer a variable that indicates which device has bus control (PCI(IDE) or DMA or CPU(lowest priority)). The DMA and PCI overruling the CPU in priority (DMA/PCI > CPU).
But is this updated per cycle? A DMA transfer may not be active when the CPU begins an instruction, but sometime after, and impact transfers for that instruction.
superfury wrote on 2024-02-24, 18:04:
Edit: Hmmm... I don't think I see pel panning so far? Are interrupts used with said demo? IRQ is lowered and vertical retrace end register is set to 10h.
The pel panning is done in the IRQ2 ISR. If the bottom window is moving up and down smoothly, you should already be handling that...
The bottom window is moving up and down, but it looks to be in character clocks or something like that?
I don't ever see it writing the PEL panning register at all.
The bottom window seems to be at odd locations though (during the island the final row seems to be displaying a part of the (last?) scanline only. Then, showing the island shows a weird bottom screen? It isn't hidden?
UniPCemu triggers IRQ2 on XT machines (9 on AT).
IRQ2 is raised when vertical retrace starts, with Vertical Retrace end register bit 4 set and bit 5 cleared (setting the flipflop). It's set and not changing afterwards?
Clearing Vertical Retrace End register bit 4 clears the interrupt flipflop.
The flipflop being set(1)/cleared(0) is reported on Input Status #0 register bit 7, inverted on EGA (not on (S)VGA).