I don't know if there's been enough of us running UMC CPU to full characterise the compatibility envelope, so I'd say to test with an Intel DX to see if it's a UMC specific thing or not.

demiurge wrote on 2024-03-21, 03:38:

Before I completely discard this board, is there something I should try?

As suggested, test with other cpus.
Update BIOS. Maybe look for some beta specific to this issue.

https://theretroweb.com/motherboards/?name=m912

BitWrangler wrote on 2024-03-21, 04:05:

I don't know if there's been enough of us running UMC CPU to full characterise the compatibility envelope, so I'd say to test with an Intel DX to see if it's a UMC specific thing or not.

Same problem with an Intel DX2 installed

demiurge wrote on 2024-03-21, 11:27:

BitWrangler wrote on 2024-03-21, 04:05:

I don't know if there's been enough of us running UMC CPU to full characterise the compatibility envelope, so I'd say to test with an Intel DX to see if it's a UMC specific thing or not.

Same problem with an Intel DX2 installed

What's your bios version?
Could you post a pic of your board?

So I was using 128kx8 DIP modules for cache as well as the tag. The manual specifies a 64x8 DIP for tag, could this be the cause? I though I could always use a bigger tag than needed.
However, once again, the 128kx8 tag works for tag in 512kB mode and that only needs a 32x8, so I don't know.

The BIOS version is 40-E300-001437-00111111-121593-GREEN-H date: 07/08/1994 and if I need to flash it can someone recommend a tool to do that?

There also seems to be some weirdness going on, but that could be the I/O controller.

demiurge wrote on 2024-04-20, 23:49:

So I was using 128kx8 DIP modules for cache as well as the tag. The manual specifies a 64x8 DIP for tag, could this be the cause […]
Show full quote

So I was using 128kx8 DIP modules for cache as well as the tag. The manual specifies a 64x8 DIP for tag, could this be the cause? I though I could always use a bigger tag than needed.
However, once again, the 128kx8 tag works for tag in 512kB mode and that only needs a 32x8, so I don't know.

The BIOS version is 40-E300-001437-00111111-121593-GREEN-H date: 07/08/1994 and if I need to flash it can someone recommend a tool to do that?

There also seems to be some weirdness going on, but that could be the I/O controller.

The exact version of your board is written next to the keyboard connector.
My guess is ver 1.4, and there are newer bios versions available.

As a tool you probably need a software, try https://theretroweb.com/drivers/75
If it doesn't work probably your bios chip is not flashable and need a new one.

Edit:

your jp10 is set to 1-2, not 2-3
jp12 should be capped
I can't see if jp5 is correctly populated, 2-3 / 4-5 / 6-7

Ok, it's 512K of L2. Picture is blurry.
Well, try updating the bios.

Nexxen wrote on 2024-04-21, 11:36:

The exact version of your board is written next to the keyboard connector. My guess is ver 1.4, and there are newer bios version […]
Show full quote

demiurge wrote on 2024-04-20, 23:49:

So I was using 128kx8 DIP modules for cache as well as the tag. The manual specifies a 64x8 DIP for tag, could this be the cause […]
Show full quote

So I was using 128kx8 DIP modules for cache as well as the tag. The manual specifies a 64x8 DIP for tag, could this be the cause? I though I could always use a bigger tag than needed.
However, once again, the 128kx8 tag works for tag in 512kB mode and that only needs a 32x8, so I don't know.

The BIOS version is 40-E300-001437-00111111-121593-GREEN-H date: 07/08/1994 and if I need to flash it can someone recommend a tool to do that?

There also seems to be some weirdness going on, but that could be the I/O controller.

The exact version of your board is written next to the keyboard connector.
My guess is ver 1.4, and there are newer bios versions available.

As a tool you probably need a software, try https://theretroweb.com/drivers/75
If it doesn't work probably your bios chip is not flashable and need a new one.

Edit:

your jp10 is set to 1-2, not 2-3
jp12 should be capped
I can't see if jp5 is correctly populated, 2-3 / 4-5 / 6-7

Ok, it's 512K of L2. Picture is blurry.
Well, try updating the bios.

I already tried using uniflash but I think the 486s need a external machine to do it.

demiurge wrote on 2024-04-21, 13:50:

I already tried using uniflash but I think the 486s need a external machine to do it.

If you have a spare bios try using that.
PCChips used write once chips.

I have a TL-886+, used it so many times it basically paid off for itself over and over again.
There is a newer version with a ton of adapters, but it's like 70€

It could be some Mask-ROM with a forged AMI sticker 🙁
Is the chip made of ceramic or plastic?

...if it´s not troublesome, it´s simply not PC-Chips.

majestyk wrote on 2024-04-21, 15:24:

It could be some Mask-ROM with a forged AMI sticker 🙁
Is the chip made of ceramic or plastic?

...if it´s not troublesome, it´s simply not PC-Chips.

PC-Chips could be one of the companies in Fallout... 🤣

Did you check to see that the manufacturer actually connected all the address lines to the cache sockets?

demiurge wrote on 2024-04-20, 23:49:

So I was using 128kx8 DIP modules for cache as well as the tag. The manual specifies a 64x8 DIP for tag, could this be the cause […]
Show full quote

So I was using 128kx8 DIP modules for cache as well as the tag. The manual specifies a 64x8 DIP for tag, could this be the cause? I though I could always use a bigger tag than needed.
However, once again, the 128kx8 tag works for tag in 512kB mode and that only needs a 32x8, so I don't know.

The BIOS version is 40-E300-001437-00111111-121593-GREEN-H date: 07/08/1994 and if I need to flash it can someone recommend a tool to do that?

There also seems to be some weirdness going on, but that could be the I/O controller.

Your cache jumper settings are wrong on this picture. For 1MB of cache (two cache banks populated) JP10 must be at 2-3 position (yours is at 1-2) and JP11 must be shorted too (yours is missing):

P.S. Your board probably is not revision 1.4. Cache jumper header JP5 seems to not be in its full length. As newer is the revision of this board as cra**ier it is.

analog_programmer wrote on 2024-05-09, 07:10:

Your cache jumper settings are wrong on this picture. For 1MB of cache (two cache banks populated) JP10 must be at 2-3 position (yours is at 1-2) and JP11 must be shorted too (yours is missing):

It was set to 512KB because the 1MB wasn't working right.

analog_programmer wrote on 2024-05-09, 07:10:

P.S. Your board probably is not revision 1.4. Cache jumper header JP5 seems to not be in its full length. As newer is the revision of this board as cra**ier it is.

It is labelled as 1.4

I have determined that the second bank just isn't working at all. I am going to sell this as a working 512KB board and get something with 1MB

Going from 256K cache to 1Mb on a 486 yields only about an 11% improvement (Re: 486 Cache size and speed questions) with 512k you probably are only 5% less than 1Mb...
Just going by douglars tests..... not sure why 1Mb cache be important on a 486, seems overkill 😀 Ask douglar what board that is....

Horun wrote on 2024-05-10, 01:32:

Going from 256K cache to 1Mb on a 486 yields only about an 11% improvement (Re: 486 Cache size and speed questions) with 512k you probably are only 5% less than 1Mb...
Just going by douglars tests..... not sure why 1Mb cache be important on a 486, seems overkill 😀 Ask douglar what board that is....

It's cool to max out your favourite retro platform. 1MB is the maximum for most 486 chipsets. Putting the most memory in is also a big challenge (without having to reduce timing values).
At least that is my motivation.

demiurge wrote on 2024-05-09, 23:50:

It was set to 512KB because the 1MB wasn't working right.

It is labelled as 1.4

I have determined that the second bank just isn't working at all. I am going to sell this as a working 512KB board and get something with 1MB

Ahhh, now I see. I'm sorry, I just tried to help by what I saw on the picture with presented jumper settings. I have M912 mobo version 1.4 too and it's equipped with 256 kB of cache SRAM in two banks which seems to be enough for 486 system with 8 MB of RAM or even 16 MB RAM (I've not tried 16 MB RAM configuration). If I'm not totally blind, it seems to me that on your board the first pin of the JP5 is missing, thus it can not be set for 256 kB cache configuration. Version 1.4 (maybe the first one) was not intended to be sold with fake cache chips, so it is a good 486 motherboard. Some boards from version 1.7 came with fake chips, but at least the pins of the sockets for cache SRAM chips are connected with traces, so ver.1.7 is OK too (a matter of replacing of fake chips with real ones). Later versions are total cr*p with directly soldered fake chips to the board and no connections to/from them.

I don't think this board will benefit much more from 1 MB of cache, but it's always cool to max-out the things 😀 Keep on trying, maybe the BIOS version is the culprit for the cache problem. There are two BIOSes for this board with couple of revisions each - AMI and Award. I like the Award one, it seems to be more feature rich and more stable.

I wonder if a "res network" (long big black ones) is missing or something.
L2 cache goes through it for a fact. 1MB was overkill and unlikely to be populated, they could have not soldered the required network.

Comparing yours with ver 1.7 could be a last step.

demiurge wrote on 2024-04-20, 23:49:

So I was using 128kx8 DIP modules for cache as well as the tag. The manual specifies a 64x8 DIP for tag, could this be the cause? I though I could always use a bigger tag than needed.
However, once again, the 128kx8 tag works for tag in 512kB mode and that only needs a 32x8, so I don't know.

On occasion, I have come across motherboards which didn't work well with a 128kx8 TAG, yet worked fine with 64kx8 TAG. This is in reference to 1024K total. I just accepted it and never bothered to figure out why. If you are looking for a PCI based socket 3 which handles 1024K well, have you considered the M919 v3.4 with the home brew 1024K cache module?