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First post, by danoon

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I hope you don't mind that I keep asking questions about the normal core implementation.

cpu\core_normal\prefix_0f.h

CASE_0F_W(0xb7) /* MOVZX Gw,Ew */
CASE_0F_W(0xbf) /* MOVSX Gw,Ew */
		{
			GetRMrw;
			if (rm >= 0xc0 ) {GetEArw;*rmrw=*earw;}
			else {GetEAa;*rmrw=LoadMw(eaa);}
			break;
		}

In the intel manual at http://www.intel.com/Assets/PDF/manual/253666.pdf it talks about:

0F B7 /r MOVZX r32,r/m16
Move word to doubleword, zero-extension.

0F BF /r MOVSX r32,r/m16
Move word to doubleword, with sign-extension.

It seems to mean the implemenation in dosbox should be

CASE_0F_W(0xb7) /* MOVZX Gd,Ew */	
		{
			GetRMrd;
			if (rm >= 0xc0 ) {GetEArw;*rmrd=*earw;}
			else {GetEAa;*rmrd=LoadMw(eaa);}
			break;
		}
                break;
CASE_0F_W(0xbf) /* MOVSX Gd,Ew */
		{
			GetRMrd;
			if (rm >= 0xc0 ) {GetEArw;*rmrd=(Bits16s)*earw;}
			else {GetEAa;*rmrd=LoadMw(eaa);}
			break;
		}

GetRMrw was changed to GetRMrd and the movsx added a (Bit16s) cast.

Any thoughts on this?

Reply 2 of 5, by wd

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I hope you don't mind that I keep asking questions about the normal core implementation.

No that's certainly appreciated.

Ah, I think I read the manual wrong

Actually it looks to me as if there is no word-word instruction but only word dword
for the 0x0f 0xb7 and 0x0f 0xbf opcodes when reading the intel/amd docs.
Sandpile has the encoding like what dosbox currently does, so just from the
resources it's not clear to me what's right (bochs seems to follow the intel
specs but their stuff is crypting nowadays).

Reply 5 of 5, by taiken7

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I recall trying to use Bochs for a disassembly project many years ago, and it turned out that the decoding was incorrect (I ended up coupling to Nasm to get the correct disassembly). So I would suggest that as a good reference.

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