| |
|
| [General Information]
|
| Processor Name: | Intel Pentium-75
|
| Current Processor Frequency: | 75.2 MHz
|
| Current Processor Frequency [MHz]: | 75
|
| | |
|
| CPU ID: | 00000525
|
| CPU Vendor: | GenuineIntel
|
| CPU Stepping: | C1/C2 / mA1 (P54LM-VRT) / P54CQS
|
| CPU Code Name: | P54C
|
| CPU Technology: | 600 nm
|
| CPU Platform: | Socket 5 (PGA-320)
|
| | |
|
| Number of CPU Cores: | 1
|
| Number of Logical CPUs: | 1
|
| | |
|
| [Operating Points]
|
| CPU Current: | 75.2 MHz
|
| | |
|
| CPU Bus Type: | FSB
|
| | |
|
| [Cache and TLB]
|
| L1 Cache: | Instruction: 8 KBytes, Data: 8 KBytes
|
| Instruction TLB: | Unknown
|
| Data TLB: | Unknown
|
| | |
|
| [Standard Feature Flags]
|
| FPU on Chip | Present
|
| Enhanced Virtual-86 Mode | Present
|
| I/O Breakpoints | Present
|
| Page Size Extensions | Present
|
| Time Stamp Counter | Present
|
| Pentium-style Model Specific Registers | Present
|
| Physical Address Extension | Not Present
|
| Machine Check Exception | Present
|
| CMPXCHG8B Instruction | Present
|
| APIC On Chip / PGE (AMD) | Not Present
|
| Fast System Call | Not Present
|
| Memory Type Range Registers | Not Present
|
| Page Global Feature | Not Present
|
| Machine Check Architecture | Not Present
|
| CMOV Instruction | Not Present
|
| Page Attribute Table | Not Present
|
| 36-bit Page Size Extensions | Not Present
|
| Processor Number | Not Present
|
| CLFLUSH Instruction | Not Present
|
| Debug Trace and EMON Store | Not Present
|
| Internal ACPI Support | Not Present
|
| MMX Technology | Not Present
|
| Fast FP Save/Restore (IA MMX-2) | Not Present
|
| Streaming SIMD Extensions | Not Present
|
| Streaming SIMD Extensions 2 | Not Present
|
| Self-Snoop | Not Present
|
| Multi-Threading Capable | Not Present
|
| Automatic Clock Control | Not Present
|
| IA-64 Processor | Not Present
|
| Signal Break on FERR | Not Present
|
| Virtual Machine Extensions (VMX) | Not Present
|
| Safer Mode Extensions (Intel TXT) | Not Present
|
| Streaming SIMD Extensions 3 | Not Present
|
| Supplemental Streaming SIMD Extensions 3 | Not Present
|
| Streaming SIMD Extensions 4.1 | Not Present
|
| Streaming SIMD Extensions 4.2 | Not Present
|
| AVX Support | Not Present
|
| Fused Multiply Add (FMA) | Not Present
|
| Carryless Multiplication (PCLMULQDQ)/GFMUL | Not Present
|
| CMPXCHG16B Support | Not Present
|
| MOVBE Instruction | Not Present
|
| POPCNT Instruction | Not Present
|
| XSAVE/XRSTOR/XSETBV/XGETBV Instructions | Not Present
|
| XGETBV/XSETBV OS Enabled | Not Present
|
| Float16 Instructions | Not Present
|
| AES Cryptography Support | Not Present
|
| Random Number Read Instruction (RDRAND) | Not Present
|
| Extended xAPIC | Not Present
|
| MONITOR/MWAIT Support | Not Present
|
| Thermal Monitor 2 | Not Present
|
| Enhanced SpeedStep Technology | Not Present
|
| L1 Context ID | Not Present
|
| Send Task Priority Messages Disabling | Not Present
|
| Processor Context ID | Not Present
|
| Direct Cache Access | Not Present
|
| TSC-deadline Timer | Not Present
|
| Performance/Debug Capability MSR | Not Present
|
| IA32 Debug Interface Support | Not Present
|
| 64-Bit Debug Store | Not Present
|
| CPL Qualified Debug Store | Not Present
|
| | |
|
| [Enhanced Features]
|
| Thermal Monitor 1: | Not Supported
|
| Thermal Monitor 2: | Not Supported
|
| Enhanced Intel SpeedStep (GV3): | Not Supported
|
| Bi-directional PROCHOT#: | N/A
|
| Extended Auto-HALT State C1E: | Not Supported
|
| MLC Streamer Prefetcher | Not Supported
|
| MLC Spatial Prefetcher | Not Supported
|
| DCU Streamer Prefetcher | Not Supported
|
| DCU IP Prefetcher | Not Supported
|
| Intel Dynamic Acceleration (IDA) Technology: | Not Supported
|
| Intel Dynamic FSB Switching: | Not Supported
|
| Intel Turbo Boost Technology: | Not Supported
|
| Programmable Ratio Limits: | Not Supported
|
| Programmable TDC/TDP Limits: | Not Supported
|
| Hardware Duty Cycling: | Not Supported
|
| | |
|
| [Memory Ranges]
|
| Maximum Physical Address Size: | 32-bit (4 GBytes)
|
| Maximum Virtual Address Size: | 32-bit (4 GBytes)
|
| |
|
| [General Information]
|
| Device Name: | SiS 5511 Chipset - Host-to-PCI Bridge
|
| Original Device Name: | SiS 5511 Chipset - Host-to-PCI Bridge
|
| Device Class: | Host-to-PCI Bridge
|
| Revision ID: | 0
|
| PCI Address (Bus:Device:Function) Number: | 0:0:0
|
| PCI Latency Timer: | 0
|
| Hardware ID: | PCI\VEN_1039&DEV_5511&SUBSYS_00000000&REV_00
|
| | |
|
| [System Resources]
|
| Interrupt Line: | N/A
|
| Interrupt Pin: | N/A
|
| | |
|
| [Features]
|
| Bus Mastering: | Enabled
|
| Running At 66 MHz: | Not Capable
|
| Fast Back-to-Back Transactions: | Not Capable
|
| | |
|
| [L2 Cache Control]
|
| L2 Cache: | Present
|
| L2 Cache Status: | Enabled
|
| SRAM Type: | Asynchronous SRAM
|
| L2 Cache Policy: | Write-Back
|
| L2 Cache Size: | 256 KByte
|
| CPU L1 Cache Write Back Mode: | Enabled
|
| Asynchronous SRAM Leadoff Timing: | Read:3, Write:3 CPUCLKs
|
| Asynchronous SRAM Burst Timing: | 2 CPUCLK
|
| Synchronous SRAM Leadoff Timing: | 3 CPUCLK
|
| Cache Burst Addressing Support: | Toggle Mode
|
| Cache Tag Size Selection: | 7 bits
|
| Cache Sizing: | Normal Operation
|
| | |
|
| [DRAM Timing Control]
|
| FP DRAM CAS Recharge Time: | 1 CPUCLK
|
| EDO Cycle CAS Pulse Width: | Read:1, Write:2 CPUCLKs
|
| EDO CAS Precharge Time: | 1 CPUCLK
|
| MDLE Timing When EDO DRAM Is Read: | 1 CPUCLK
|
| BRDY# Timing when EDO DRAM Is Read: | 1 CPUCLK
|
| DRAM RAS-to-CAS Delay Timing: | 4 CPUCLK
|
| DRAM RAS Precharge Timing (FPM): | 3 CPUCLK
|
| RAS Active When Refresh: | 4 CPUCLK
|
| RAS Precharge Timing For (EDO): | 3 CPUCLK
|
| CAS Output Delay (HD to CTMFF): | 1 CPUCLK
|
| DRAM Bank-Interleave Mode: | Non-interleave
|
| Always Page Miss Mode in DRAM Read Cycle: | Normal mode
|
| RAMW# Power Saving Mode While EDO Access: | Normal mode
|
| NA# Disable: | Disabled
|
| EDO Test Mode: | Normal Mode
|
| Pipelined Burst SRAM / Burst SRAM Test Mode: | Normal Mode
|
| Slow Refresh (1:4): | Enabled
|
| Deturbo: | Enabled
|
| FLUSH# / INTR1 Selection: | FLUSH#
|
| CPUID / Turbo Selection: | Turbo
|
| RAS[3:0]# Current Rating Selection: | 8 mA
|
| | |
|
| [Non-Cacheable Area I]
|
| Allocation of Non-Cacheable Area I: | PCI Bus
|
| Non-Cacheable Area I Status: | Disabled
|
| Non-Cacheable Area I Size: | 1 MB
|
| Non-Cacheable Area I [26:24]: | 0
|
| Non-Cacheable Area I: | F00000
|
| | |
|
| [Non-Cacheable Area II]
|
| Allocation of Non-Cacheable Area II: | Local DRAM
|
| Non-Cacheable Area II Status: | Disabled
|
| Non-Cacheable Area II Size: | 64 KB
|
| Non-Cacheable Area II [26:24]: | 0
|
| Non-Cacheable Area II: | 0
|
| | |
|
| [CPU-to-PCI Characteristics]
|
| Fast Gate A20 Emulation: | Enabled
|
| Fast Reset Emulation: | Enabled
|
| Fast Reset Latency: | 6 us
|
| IDE Prefetching Function: | Disabled
|
| CPU-to-PCI Post Write Rate: | 4 CPUCLKs
|
| Disarming of 'Full' to BRDY# Latency: | 1 CPUCLKs
|
| CPU-to-PCI Burst Memory Write: | Enabled
|
| CPU-to-PCI Post Memory Write: | Enabled
|
| | |
|
| [PCI Master Characteristics]
|
| DRAM Refresh Cycle In PCI Master Cycles: | Disabled
|
| Maximum Burstable Address Range: | 4 KB
|
| TRDY# Assertion Timing In PCI Master Read Cycle: | After 2 Qws
|
| Advanced Snoop In PCI Master Write Cycle: | Enabled
|
| Advanced Snoop In PCI Master Read Cycle: | Disabled
|
| CPU to L2/DRAM and PCI Peer-to-Peer Concurrency: | Disabled
|
| KWE# Synchronization Clock: | CPUCLK
|
| Pshmd of HCR[3:0] Timing Control (EDO): | 1 CPUCLK
|
| Pshmd of HCR[3:0] Timing Control (FPM): | 1 CPUCLK
|
| Retiring Tate From PTHFF To EDO: | 3 CPUCLKs
|
| Prefetching Rate From EDO in PCI Master Read Cycle: | 2 CPUCLKs
|
| | |
|
| [DRAM Signals Driving Current Control]
|
| AD[31:0] Current Rating: | 50 mA/2.2 V
|
| FRAME#, IRDY#, TRDY#... Current Rating: | 50 mA/2.2 V
|
| GNT[3:0]#, PAR Current Rating: | 50 mA/2.2V
|
| CASE[7:0]# Buffer Strength: | 5 V
|
| CASE[7:0]# Current Rating: | 8 mA
|
| CASO[7:0]# Buffer Strength: | 5 V
|
| CASO[7:0]# Current Rating: | 8 mA
|
| RAS[3:0]# Buffer Strength: | 5 V
|
| | |
|
| [Counter Reload]
|
| Reload On Programmable 10-bit I/O Port Access: | Disabled
|
| Reload On Programmable 16-bit I/O Port Access: | Disabled
|
| Reload On Hard Disk Port Access: | Enabled
|
| Reload On Serial Port Access: | Enabled
|
| Reload On Parallel Port Access: | Enabled
|
| Reload On HOLD: | Enabled
|
| Reload On IRQ1-15, NMI: | Enabled
|
| | |
|
| [Monitor Standby Timer]
|
| Reload On IRQ 1-15, NMI: | Disabled
|
| Reload On HOLD: | Disabled
|
| Return To Normal State On IRQ 1-15, NMI: | Disabled
|
| Return To Normal State On HOLD: | Disabled
|
| De-assert STPCLK# On IRQ 1-15, NMI: | Enabled
|
| De-assert STPCLK# On HOLD: | Enabled
|
| De-assert STPCLK# On INIT: | Enabled
|
| STPCLK#: | Disabled
|
| Throttling: | Disabled
|
| STPCLK# Control: | Disabled
|
| Break Switch Selection: | BREAK#
|
| | |
|
| [STPCLK# Assertion Timer]
|
| STPCLK# Assertion Timer: | 2
|
| | |
|
| [STPCLK# De-assertion Timer]
|
| STPCLK# De-assertion Timer: | 2
|
| | |
|
| [System Standby Timer]
|
| System Standby Timer: | 255
|
| | |
|
| [Cyrix 6x86 and PMU Function Control]
|
| Cyrix 6x86 SMAC Access: | Disabled
|
| Cyrix 6x86 MMAC Access: | Disabled
|
| Cyrix 6x86 CPU: | Not present
|
| Toggle Mode: | Disabled
|
| Flush Function Block Mode: | Un-block
|
| WAKEUP0 / ALT Selection: | ALT
|
| SMOUT / RAS2# Selection: | SMOUT
|
| SMRAM Area: | E0000h - E7FFFh
|
| SMRAM Access Outside SMI Handler: | Disabled
|
| | |
|
| [Time Slot and Programmable 10-bit I/O Port Definition]
|
| Monitor Standby Time Slot: | 6.6 s
|
| Programmable 10-bit I/O Port Address Mask: | No mask
|
| Programmable 10-bit I/O Port Address [0:1]: | 0
|
| Programmable 10-bit I/O Port Address [9:2]: | FF
|
| | |
|
| [Wake-up Enable]
|
| System Standby SMI: | Disabled
|
| Programmable 10-bit I/O Port Wake Up SMI: | Disabled
|
| Programmable 16-bit I/O port Wake Up SMI: | Disabled
|
| Serial Port Wake Up SMI: | Disabled
|
| Parallel Port Wake Up SMI: | Disabled
|
| Hard Disk Port SMI: | Disabled
|
| Break Switch SMI: | Disabled
|
| Software SMI: | Disabled
|
| | |
|
| [Wake-up Request]
|
| System Standby SMI Request: | Disabled
|
| Programmable 10-bit I/O Port Wake Up Request: | Disabled
|
| Programmable 16-bit I/O port Wake Up Request: | Disabled
|
| Serial Port Wake up Request: | Disabled
|
| Parallel Port Wake Up Request: | Disabled
|
| Hard Disk Port Wake Up Request: | Disabled
|
| Break Switch SMI Request: | Disabled
|
| Software SMI Request: | Disabled
|
| Monitor Standby SMI: | Disabled
|
| Monitor Wake Up SMI: | Disabled
|
| Monitor Wake Up Request: | Disabled
|
| Throttling Wake Up SMI Request: | Inactive
|
| Throttling Wake Up SMI: | Disabled
|
| System Wake Up SMI: | Disabled
|
| System Wake Up SMI Request: | Inactive
|
| | |
|
| [Monitor Standby Timer]
|
| Monitor Standby Timer: | FFFF
|
| | |
|
| [Programmable 16-bit I/O Port]
|
| Programmable 16-bit I/O Port: | FFFF
|
| | |
|
| [Port Trap]
|
| A0000h-AFFFFh / B0000-BFFFFh Address Trap: | Disabled
|
| C0000h-C7FFFh Address Trap: | Disabled
|
| 3B0-3BFh, 3C0-3CFh, 3D0-3DFh Address Trap: | Disabled
|
| Secondary Drive Port Trap: | Enabled
|
| System Standby Timer Slot: | 9 s
|
| | |
|
| [Shadow RAM Control]
|
| 0C0000h-0C3FFFh Shadow RAM: | Read-only, cacheable
|
| 0C4000h-0C7FFFh Shadow RAM: | Read-only, cacheable
|
| 0C8000h-0CBFFFh Shadow RAM: | No Access
|
| 0CC000h-0CFFFFh Shadow RAM: | No Access
|
| 0D0000h-0D3FFFh Shadow RAM: | No Access
|
| 0D4000h-0D7FFFh Shadow RAM: | No Access
|
| 0D8000h-0DBFFFh Shadow RAM: | No Access
|
| 0DC000h-0DFFFFh Shadow RAM: | No Access
|
| 0E0000h-0E3FFFh Shadow RAM: | Read-only, not-cacheable
|
| 0E4000h-0E7FFFh Shadow RAM: | Read-only, not-cacheable
|
| 0E8000h-0EBFFFh Shadow RAM: | Read-only, not-cacheable
|
| 0EC000h-0EFFFFh Shadow RAM: | Read-only, not-cacheable
|
| | |
|
| [BIOS Shadow Control]
|
| BIOS 0F0000-0FFFFF Read: | Enabled
|
| BIOS 0F0000-0FFFFF Caching: | Enabled
|
| BIOS 0F0000-0FFFFF Write: | Disabled
|
| Shadow RAM For PCI Master Access: | Disabled
|
| |
|
| [General Information]
|
| Device Name: | SiS 5595 PCI-to-ISA Bridge [A2]
|
| Original Device Name: | SiS 5595 PCI-to-ISA Bridge [A2]
|
| Device Class: | PCI-to-ISA Bridge
|
| Revision ID: | 1
|
| PCI Address (Bus:Device:Function) Number: | 0:1:0
|
| PCI Latency Timer: | 0
|
| Hardware ID: | PCI\VEN_1039&DEV_0008&SUBSYS_00000000&REV_01
|
| | |
|
| [System Resources]
|
| Interrupt Line: | N/A
|
| Interrupt Pin: | N/A
|
| | |
|
| [Features]
|
| Bus Mastering: | Enabled
|
| Running At 66 MHz: | Not Capable
|
| Fast Back-to-Back Transactions: | Not Capable
|
| | |
|
| [BIOS Control Register]
|
| ACPI State: | Disabled
|
| PCI Delayed Transaction: | Disabled
|
| PCI Posted Write Buffer: | Disabled
|
| Positive Decode of Upper 64K BIOS: | Enabled
|
| BIOS Subtractive Decode: | Disabled
|
| Lower BIOS: | Enabled
|
| Extended BIOS (FFF80000-FFFDFFFF): | Disabled
|
| | |
|
| [INTA# Remapping Control]
|
| Remapping Control: | Disabled
|
| IRQ Remapping: | IRQ0
|
| | |
|
| [INTB# Remapping Control]
|
| Remapping Control: | Enabled
|
| IRQ Remapping: | IRQ9
|
| | |
|
| [INTC# Remapping Control]
|
| Remapping Control: | Disabled
|
| IRQ Remapping: | IRQ0
|
| | |
|
| [INTD# Remapping Control]
|
| Remapping Control: | Disabled
|
| IRQ Remapping: | IRQ0
|
| | |
|
| [ISA Bus Control Register I]
|
| ISA Bus Clock Select: | 7.159 MHz
|
| Flash EPROM Control 0: | Disabled
|
| RTC Extended Bank: | Disabled
|
| Flash EPROM Control 1: | Disabled
|
| Automatic Power Control Registers: | Disabled
|
| | |
|
| [ISA Bus Control Register II]
|
| 16-bit I/O Cycle Command Recovery Time: | 5 BUSCLKs
|
| 8-bit I/O Cycle Command Recovery Time: | 8 BUSCLKs
|
| ROM Cycle Wait State Selection: | 4 WS
|
| | |
|
| [DMA Clock and Wait State Control Register]
|
| Extended Terminal Count (TC)Hold Time: | i8237 compatible
|
| 16-bit DMA Cycle Wait State: | 1 DMACLKs
|
| 8-bit DMA Cycle Wait State: | 1 DMACLKs
|
| Extended DMAMEMR# Control: | Enabled
|
| DMA Clock: | ISA BUSCLK/2
|
| | |
|
| [ISA Master/DMA Memory Cycle Control 1]
|
| Top Of ISA Memory: | 16 MBytes
|
| Forward E0000h-EFFFFh Access To PCI Bus: | Enabled
|
| Forward A0000h-BFFFFh Access To PCI Bus: | Enabled
|
| Forward 80000h-9FFFFh Access To PCI Bus: | Enabled
|
| Forward 00000h-7FFFFh Access To PCI Bus: | Enabled
|
| | |
|
| [ISA Master/DMA Memory Cycle Control 2]
|
| Forward DC000h-DFFFFh Access To PCI Bus: | Enabled
|
| Forward D8000h-DBFFFh Access To PCI Bus: | Enabled
|
| Forward D4000h-D7FFFh Access To PCI Bus: | Enabled
|
| Forward D0000h-D3FFFh Access To PCI Bus: | Enabled
|
| Forward CC000h-CFFFFh Access To PCI Bus: | Enabled
|
| Forward C8000h-CBFFFh Access To PCI Bus: | Enabled
|
| Forward C4000h-C7FFFh Access To PCI Bus: | Enabled
|
| Forward C0000h-C3FFFh Access To PCI Bus: | Enabled
|
| | |
|
| [ISA Memory Hole]
|
| ISA Memory Hole Bottom: | 100000
|
| ISA Memory Hole Top: | F0000
|
| | |
|
| [Shadow Registers]
|
| ICW1-ICW4 (INT1) Shadow Register: | 1045011
|
| ICW1-ICW4 (INT2) Shadow Register: | 1025811
|
| OCW2-OCW3 (INT1) Shadow Register: | A62
|
| OCW2-OCW3 (INT2) Shadow Register: | A66
|
| CTC Counter 0 Shadow Register: | 174D
|
| CTC Counter 1 Shadow Register: | 12
|
| Built-in CTC Shadow Register: | 50
|
| | |
|
| [MIRQ0 Remapping Control Register]
|
| MIRQ0 Remapping: | Disabled
|
| MIRQ0/IRQx Sharing: | Enabled
|
| Interrupt Remapping: | IRQ0
|
| | |
|
| [MIRQ1 Remapping Control Register]
|
| MIRQ1 Remapping: | Disabled
|
| MIRQ1/IRQx Sharing: | Enabled
|
| Interrupt Remapping: | IRQ0
|
| | |
|
| [On-board Device DMA Control]
|
| MDRQ1/MDACK1# Remapping: | Disabled
|
| DMA Channel Remapping of MDRQ1/MDACK1#: | Channel 4
|
| MDRQ0/MDACK0# Remapping: | Disabled
|
| DMA Channel Remapping of MDRQ0/MDACK0#: | Channel 4
|
| | |
|
| [IDEIRQ Remapping Control]
|
| IDEIRQ Remapping: | Disabled
|
| Interrupt Remapping: | IRQ0
|
| | |
|
| [GPIO0 Control]
|
| GPIO0 Mode: | Output mode
|
| GPIO0 Input Active Level: | Active low
|
| GPIO0 Input Bounce-Free: | Disabled
|
| De-bounce Count for GPIO0: | 0
|
| SIO To IDE Master Arbiter: | Enabled
|
| | |
|
| [GPIO0 Output Mode Control]
|
| GPIO0 I/O Space Base Address: | 0
|
| GPIO0 I/O Space Address Mask: | Disabled
|
| | |
|
| [Data Acquisition Module Base Address]
|
| Data Acquisition Module I/O Base Address: | 2
|
| | |
|
| [GPIO Status]
|
| Arbiter Operating Mode: | Fixed priority
|
| Built-in RTC Status: | Used
|
| GPIO0 Status: | Inactive
|
| |
|
| [General Information]
|
| Device Name: | SiS 85C513 IDE Controller
|
| Original Device Name: | SiS 85C513 IDE Controller
|
| Device Class: | IDE Controller
|
| Revision ID: | 8
|
| PCI Address (Bus:Device:Function) Number: | 0:1:1
|
| PCI Latency Timer: | 0
|
| Hardware ID: | PCI\VEN_1039&DEV_5513&SUBSYS_00000000&REV_08
|
| | |
|
| [System Resources]
|
| Interrupt Line: | IRQ15
|
| Interrupt Pin: | INTA#
|
| I/O Base Address 0 | 1F0
|
| I/O Base Address 1 | 3F4
|
| I/O Base Address 2 | 170
|
| I/O Base Address 3 | 374
|
| I/O Base Address 4 | 4000
|
| | |
|
| [Features]
|
| Bus Mastering: | Enabled
|
| Running At 66 MHz: | Not Capable
|
| Fast Back-to-Back Transactions: | Not Capable
|
| | |
|
| [IDE Primary Channel/Master Drive Data Recovery Time Control]
|
| Recovery Time: | 1 PCICLK
|
| | |
|
| [IDE Primary Channel/Master Drive Data Active Time Control]
|
| Ultra DMA Mode: | Disabled
|
| Ultra DMA 33/66 cycle time: | N/A
|
| Data Active Time Control: | 3 PCICLK
|
| | |
|
| [IDE Primary Channel/Slave Drive Data Recovery Time Control]
|
| Recovery Time: | 12 PCICLK
|
| | |
|
| [IDE Primary Channel/Slave Drive Data Active Time Control]
|
| Ultra DMA Mode: | Disabled
|
| Ultra DMA 33/66 cycle time: | N/A
|
| Data Active Time Control: | 8 PCICLK
|
| | |
|
| [IDE Secondary Channel/Master Drive Data Recovery Time Control]
|
| Recovery Time: | 12 PCICLK
|
| | |
|
| [IDE Secondary Channel/Master Drive Data Active Time Control]
|
| Ultra DMA Mode: | Disabled
|
| Ultra DMA 33/66 cycle time: | N/A
|
| Data Active Time Control: | 8 PCICLK
|
| | |
|
| [IDE Secondary Channel/Slave Drive Data Recovery Time Control]
|
| Recovery Time: | 12 PCICLK
|
| | |
|
| [IDE Secondary Channel/Slave Drive Data Active Time Control]
|
| Ultra DMA Mode: | Disabled
|
| Ultra DMA 33/66 cycle time: | N/A
|
| Data Active Time Control: | 8 PCICLK
|
| | |
|
| [IDE Status Register]
|
| Channel 1 Cable Type: | 80 pins cable type
|
| Channel 0 Cable Type: | 80 pins cable type
|
| PCI Read Request Threshold Setting: | If FIFO 62.5% full
|
| PCI Write Request Threshold Setting: | If FIFO 12.5% full
|
| | |
|
| [IDE General Control 0]
|
| Burst Mode: | Disabled
|
| Test Mode: | Disabled
|
| Fast post-write control: | Disabled
|
| Secondary Channel Master PIO Mode: | Disabled
|
| Primary Channel Master PIO Mode: | Disabled
|
| IDE Secondary Channel: | Enabled
|
| IDE Primary Channel: | Enabled
|
| | |
|
| [IDE General Control 1]
|
| Reset IDE State Machine: | Disabled
|
| Secondary Channel Post Write: | Disabled
|
| Primary Channel Post Write: | Disabled
|
| Secondary Channel Master Prefetch: | Disabled
|
| Primary Channel Master Prefetch: | Disabled
|
| | |
|
| [Prefetch Counts]
|
| Primary Channel Prefetch Count: | 512
|
| Secondary Channel Prefetch Count: | 512
|